(1) Field of the Invention
This invention relates generally to voltage regulators, and more particularly to a low drop-out (LDO) voltage regulator having from zero to full load a low quiescent current, no explicit low power mode and an excellent PSRR due to load dependent bias current.
(2) Description of the Prior Art
Low-dropout (LDO) linear regulators are commonly used to provide power to low-voltage digital circuits, where point-of-load regulation is important. In these applications, it is common for the digital circuit to have different modes of operation. As the digital circuit switches from one mode of operation to another, the load demand on the LDO can change quickly. This quick change of load results in a temporary glitch of the LDO output voltage. Most digital circuits do not react favourably to large voltage transients. An important goal for voltage regulators is to isolate sensitive circuitry from the transient voltage changes of the battery.
The PSSR of the voltage regulator significantly reduces the supply transient seen by the phone circuits. Applications requiring power from LDO voltage regulators are becoming more sensitive to noise as frequency and application bandwidth are constantly increased. Therefore power supply ripple rejection (PSRR) characteristics are extremely important associated with LDO voltage regulators.
Conventional LDO regulators are very problematic in the area of transient response. The transient response is the maximum allowable output variation for a load current step change and must be frequency compensated in order to ensure a stable output voltage. Conventional means to compensate frequency dependencies are limiting the load regulation performance and the accuracy of the output.
A low quiescent or ground current is important for the efficiency of a LDO voltage regulator. FIG. 1 prior art shows the principle currents of such a LDO regulator 4 regulating the battery voltage Vbat 5. The quiescent current Iq 3 is the difference between the input current Ii 1 and output current Io 2:Iq=Ii−Io. 
Quiescent current consists of bias current (such as band-gap reference, sampling resistor, and error amplifier currents) and the gate drive current of the series pass element, which do not contribute to output power. The value of quiescent current is mostly determined by the series pass element, topologies, ambient temperature, etc.
In prior art an extra low power mode is often introduced to cover a wide output load range. FIG. 2 prior art illustrates a typical embodiment of the driver stages of such a solution. There is one driver stage for high power 21 covering an output load range e.g. from 10 mA to 140 mA. Additionally there is another driver stage for low power 22 covering an output load range from 0 mA to 10 mA. The quiescent or wasted current of the low power driver stage is relatively low but said quiescent current of the high power driver stage is typically in the order of magnitude of 100 μA. This means that at output currents above 10 mA up to 1% of the output current is wasted. Another problem is the switching required with every change from one power mode to another exposing sensitive circuits to potential malfunctions.
U.S. Pat. No. (6,246,221 B1 to Xi) describes a high power supply ripple rejection (PSRR) internally compensated low drop-out (LDO) voltage regulator using an output PMOS pass device. The voltage regulator uses a non-inversion variable gain amplifier stage to adjust its gain in response to a load current passing through the output PMOS device such that as the load current decreases, the gain increases, wherein a second pole associated with the voltage regulator is pushed above a unity gain frequency associated with the voltage regulator.
U.S. Pat. No. (6,304,131 B1 to Huggins et al) discloses a high power supply ripple rejection internally compensated low drop-out (LDO) voltage regulator using an output PMOS pass device. The voltage regulator uses an intermediate amplifier stage configured from a common source, current mirror loaded PMOS device to replace the more conventional source follower impedance buffer associated with conventional Miller compensation techniques. Compensation is achieved through the use of a small internal capacitor that provides a very low frequency dominant pole at the output of the input stage.
U.S. Pat. No. (6,340,918 B2 to Taylor et al.) shows a frequency compensation of multi-stage amplifiers circuits. Particularly, but not exclusively, the invention provides a frequency compensation scheme for negative feedback amplifiers circuits such as voltage regulators, and in particular for low drop-out (LDO) regulators. An amplifier circuit comprises a first amplifier stage controlling a second gain stage which is coupled between a voltage input node and an output node. A frequency compensating circuit is coupled between a compensating circuit node of the gain stage and a control input of the gain stage.